This invention relates to an improvement in a diagnostic check system for a digital signal circuit which leads digital signals from a processor such as a microcomputer to a controlled apparatus.
Whereas processors such as microcomputers or minicomputers treat only information or data in their internal circuits, an interface including decoders, buffers and gates and a digital signal circuit including voltage level changers must process not only information or data but also power to drive relays so that they are liable to incur faults. This tendency to easily cause faults adversely affects the reliability of the system.
To eliminate such a drawback, a variety of diagnostic check systems for a digital signal circuit have been hitherto proposed. For example, the Japanese Patent Laid-Open publication No. 50667/77 laid open for public inspection on Apr. 22, 1977 discloses a system for transmitting digital signals from a computer to a controlled apparatus through an interface including relay drivers, in which diagnostic check is performed by detecting how the output signals of the relay drivers change under the signal conditions given by the computer and then by returning the detected signals to the computer. With this diagnostic check system, however, the diagnostic check of, for example, sixteen digital circuits needs test stages having twenty conditions imposed by the computer. Moreover, since each test stage forms a diagnostic system in which two sets of relays are connected in series with each other by the relay drivers and relay receivers, much time is consumed for the diagnostic of faults due to the delays of operation of relays so that it is difficult to perform diagnostic checks in an active state of or during the operation of the controlled apparatus.